Nagpur, Maharashtra, India • Open for Engineering Roles

Ashlesha Manish Pokale

Semiconductor Devices FPGA & VHDL RTL Embedded Systems Industrial Automation

Final-year Electronics & Telecommunication Engineering undergraduate at SVPCET Nagpur. Specialized in semiconductor device characterization with NGSpice (WEL Lab, IIT Bombay), digital logic & FSM synthesis with Verilog/VHDL on Xilinx FPGA, real-time Edge-AI NPU sensor fusion, and Siemens PLC / SCADA automation.

7.70
B.Tech CGPA (6 sems)
IITB
WEL Lab (NPTEL)
10+
Engineered Systems
2nd
₹20K Project Award
fsm_sequence_1011.vhd
Xilinx Spartan-3E
// VHDL Finite State Machine: 1011 Non-overlapping Sequence
entity Sequence_Detector is
port( clk, rst, din : in std_logic;
match_out : out std_logic );
end Sequence_Detector;
// FSM States: S0 (Idle) -> S1 ('1') -> S2 ('10') -> S3 ('101') -> Match!
Live FSM State State: S0 (IDLE)
Stream Buffer: ...0000
Target Sequence: 1011
Output Flag: 0
Engineering Focus & Philosophy

Bridging Silicon Physics, Digital RTL & Edge AI Systems

I am a final-year Electronics & Telecommunication Engineering student at St. Vincent Pallotti College of Engineering & Technology, Nagpur. My core passion lies at the intersection of microscopic semiconductor physics and macroscopic digital hardware realization. From characterizing sub-micron MOSFET transfer and drain curves in NGSpice, to synthesizing complex FSM architectures on Xilinx FPGAs, to deploying real-time multi-sensor Edge AI on ARM NPUs, I build hardware that is mathematically validated, power-efficient, and engineered for mission-critical reliability.

Semiconductors

Device characterization, I-V / C-V analysis, MOSFET subthreshold slope, diode physics & NGSpice SPICE simulation at IIT Bombay WEL Lab.

Digital RTL & FPGA

VHDL / Verilog HDL modeling, Moore/Mealy FSM design, timing simulation, priority encoders, and synthesis on Xilinx Spartan-3E using ISE 14.7.

Embedded & Edge AI

ARM Cortex-M3 (STM32), ESP32, Radxa SBC with 3-TOPS Vivante NPU, 4K MIPI CSI-2 vision, sensor fusion, ADC motor protection, and LoRa wireless.

Automation & IIoT

Siemens TIA Portal PLC programming (LAD, FBD, SFC), SCADA/HMI dashboards, sensor-actuator interfacing trained at Siemens COE, VNIT Nagpur.

Final Year Major Capstone Project

Indigenous Integrated Railway Track Monitoring System (ITMS)

Contactless Edge-AI Multi-Sensor Inspection Architecture for Indian Railways

šŸ† 2nd Prize Winner
Best Project Award (Core Category)
₹20,000 Cash Prize • R&D Cell SVPCET

Engineering Motivation & Research Innovation

Conventional track inspection in Indian Railways relies on manual physical foot-patrolling or exorbitant imported Track Recording Cars (TRC) that require track closure. ITMS introduces an indigenous, contactless multi-sensor edge inspection vehicle powered by an ARM Single Board Computer (Radxa Cubie A7A with 3-TOPS Vivante NPU) executing real-time Edge-AI defect classification alongside 6-axis IMU vibration telemetry and GPS/LoRa geo-tagged alert dispatch.

Vision Payload Sony IMX415 4K MIPI CSI-2 Hardware Pipeline
Edge AI Engine Custom YOLOv8 15 Defect Classes Trained
Accuracy Metric 0.867 mAP@0.5 0.83 Prec / 0.85 Recall

Real-time Sensor-to-Cloud Execution Pipeline

1. Acquisition
4K Video + 6-Axis IMU
2. NPU Inference
3-TOPS Vivante Engine
3. Geo-Tagging
GPS NMEA Telemetry
4. LoRa Station
Sub-GHz Long Range Link
Engineered by: Vedant Burde, Aryan Choudhari, Ashlesha Pokale, Vaibhav Varma
Project Guide: Dr. Hema Kale (Asst. Prof, ETC Dept)
Live Edge-AI Telemetry
Vivante NPU: 18.2ms / 55 FPS
CAM: SONY IMX415 (4K) REC 00:14:28.91 LIVE TRACK
Crack in Rail Head 94.2%
Severity: Medium | Loc: MP 14/2
GPS: 21.1458° N, 79.0882° E IMU: Nominal (0.12g)
6-Axis IMU Real-Time Accelerometer Trace (Z-Axis) Sampling: 200 Hz
Interactive Engineering Workbench

Hardware & Semiconductor Simulator Lab

Experience real-time hardware simulation directly in your browser: explore MOSFET device physics, test the VHDL 1011 state machine, and evaluate digital logic.

Device Characterization

MOSFET $I_D - V_{DS}$ Output Curves

Simulating the Level-1 Shichman-Hodges MOSFET equation studied and simulated at IIT Bombay WEL Lab (NPTEL). Adjust Gate Voltage ($V_{GS}$) and Threshold Voltage ($V_{th}$) to watch the operating region transition between Cutoff, Triode / Linear, and Saturation in real-time.

Gate-to-Source Voltage ($V_{GS}$): 3.0 V
Threshold Voltage ($V_{th}$): 0.8 V
Channel Length Modulation ($\lambda$): 0.02 /V
Current Region: Saturation Region
Overdrive ($V_{GS} - V_{th}$): 2.20 V
Peak Saturation Current ($I_{D,sat}$): 4.84 mA
$I_D$ (Drain Current, mA) vs. $V_{DS}$ (Drain Voltage, V) 60 FPS Real-time Engine
Active $V_{GS}$ Curve Family of $V_{GS}$ Curves (1V to 5V) $V_{DS,sat}$ Boundary Pinch-off
Comprehensive Toolchain

Technical Skills & Technologies

Semiconductor & Microelectronics

Hands-on device characterization, semiconductor physics, and circuit level SPICE modeling.

Semiconductor Devices Device Characterization I-V Analysis C-V Analysis NGSpice SPICE Simulation MOSFET / CMOS BJT Modeling
Digital RTL & FPGA Architecture

Hardware description languages, timing verification, and FPGA bitstream generation.

Verilog HDL VHDL FPGA Design Xilinx Spartan-3E Xilinx ISE 14.7 FSM Design VLSI Design DRC Rule Check
Embedded Systems & Edge Microcontrollers

Firmware architecture, low-level register configuration, and peripheral protocols.

Embedded C STM32 (Cortex-M3) STM32CubeIDE ESP32 SoC ADC & DMA Sensor Interfacing Motor Control IoT Protocols
Industrial Automation & IIoT

Siemens automation ecosystem, supervisory control, and field-level deterministic logic.

Siemens TIA Portal PLC Programming Ladder Diagram (LAD) FBD & SFC SCADA Systems HMI Design Sensor-Actuator Links
DSP, Circuit Simulation & Radar

Signal filtering, spectrum decomposition, and satellite synthetic aperture radar analysis.

MATLAB FFT Spectrum Butterworth Filters NI Multisim Proteus VSM NISAR Radar SAR GIS Telemetry
Languages & Computational Tools

Core procedural programming, scripting, and web dashboard prototyping.

C C++ Python HTML5 / CSS3 JavaScript Chart.js Linux / Shell
Engineering Portfolio

10 Engineered Systems & Research Projects

From silicon device physics and FPGA syntheses to embedded ARM firmware and industrial robotics.

Showing 10 of 10 projects
Embedded C / STM32 Aug 2026 – Sep 2026

Agricultural Motor Protection Relay Using STM32

Engineered a low-cost, solid-state agricultural motor protection relay using the STM32F103C8T6 (ARM Cortex-M3). Implemented real-time ADC multi-channel sampling for simulated 3-phase voltage and motor current to detect over/under-voltage, phase reversal, overcurrent, and dry-run faults with programmable recovery delays.

STM32CubeIDE ARM Cortex-M3 ADC DMA Fault FSM
MRSAC Internship Jun 2026

NISAR-Based Precision Agriculture Monitoring

Formulated a comprehensive technical review and IoT architecture during internship at MRSAC. Investigated NASA-ISRO Synthetic Aperture Radar (NISAR) L-band and S-band radar data integration with localized ESP32 field telemetry for automated soil moisture mapping and variable-rate irrigation.

Remote Sensing NISAR SAR ESP32 IoT Chart.js GIS
Verilog & VHDL Dec 2025 – Nov 2026

Digital Design & Verification (Verilog & VHDL)

Modeled combinational building blocks (half adders, full adders, multiplexers) in Verilog HDL. Architected and simulated a 1011 sequence detector using Mealy/Moore FSMs in VHDL with comprehensive testbench timing verification in Xilinx ISE 14.7.

Verilog HDL VHDL Xilinx ISE 14.7 Testbench Timing
FPGA Synthesis Dec 2025 – May 2026

FPGA-Based Digital System Design using VHDL

Synthesized and verified multi-module digital systems targeted for the Xilinx Spartan-3E FPGA. Implemented 8-to-3 priority encoders, 4-bit universal shift registers, synchronous up/down binary counters, and modular Arithmetic Logic Units (ALUs).

Spartan-3E FPGA ALU Modular RTL Shift Registers Synthesis DRC
IIT Bombay WEL Lab Jun 2026

Semiconductor Device Simulation & Characterization

Extracted device physics parameters via NGSpice: simulated diode/Schottky forward/reverse I-V characteristics, NMOS/PMOS transfer and drain families, CMOS inverter voltage transfer curves (VTC), subthreshold slope, and MOS capacitor C-V profiling.

NGSpice MOSFET C-V CMOS Inverter Subthreshold
DSP Simulation Jul 2025 – Nov 2025

Sleep Apnea Detection using MATLAB

Formulated digital signal processing algorithms in MATLAB to detect obstructive sleep apnea events. Implemented synthetic respiratory airflow synthesis, noise corruption, Butterworth bandpass filtering, and spectral power FFT peak extraction.

MATLAB FFT Spectrum Butterworth Biomedical DSP
IoT System Jul 2025 – Nov 2025

Smart Parking System (ESP32)

Built an automated vehicular parking occupancy monitor using active infrared sensors connected to an ESP32 microcontroller. Displays real-time vacant slots and directional guidance on an I2C LCD screen and web portal.

ESP32 IR Sensors I2C LCD IoT State
IIT Bombay TechFest Dec 2024

Obstacle Avoidance Autonomous Robot

Competed at IIT Bombay TechFest 2024 with a self-navigating mobile robot built on Arduino and dual IR range sensors. Programmed real-time collision avoidance and dynamic differential steering PWM control.

Arduino H-Bridge L298N Differential Drive
NI Multisim Circuit Jul 2024 – Nov 2024

Fire Alarm System Simulation & Prototype

Designed and simulated automated fire and thermal threshold detection schematics in NI Multisim. Fabricated breadboard prototype with thermal/optical sensors and dual-state audio/visual latching circuitry.

NI Multisim Analog Schematics Hardware PCB
Competition Chassis Feb 2024

Robo Race Vehicle (High-Torque Chassis)

Engineered a high-torque robotic racing chassis featuring dual wired and 2.4 GHz wireless RF control modes, optimized center of gravity, high-RPM DC geared motors, and low-latency steering control.

High-RPM Motors 2.4GHz RF Mechanical Chassis
Career Pathway

Research & Industrial Experience

Real-world engineering internships in remote sensing research and industrial automation.

Research Intern

Maharashtra Remote Sensing Application Centre (MRSAC), Nagpur
Jun 2026 • 1 Month
  • Conducted deep technical investigation into NASA-ISRO Synthetic Aperture Radar (NISAR) multi-frequency SAR applications in precision agriculture.
  • Analyzed the integration of GIS spatial layers, satellite remote sensing, and localized ESP32 IoT sensors for telemetry-driven irrigation logic.
  • Engineered an interactive geospatial web telemetry dashboard utilizing HTML5, CSS3, JavaScript, and Chart.js simulating real-time field sensors.
NISAR SAR Remote Sensing GIS Telemetry ESP32 IoT

Industrial Automation with IIoT Intern

V. R. Jamdar Siemens Center of Excellence, VNIT Nagpur
Jun 2025 • 1 Month
  • Configured programmable logic controllers using Siemens TIA Portal across Ladder Diagram (LAD), Function Block Diagram (FBD), and Sequential Function Chart (SFC).
  • Developed industrial supervisory control and data acquisition (SCADA) and HMI interfaces for continuous monitoring of automated assembly lines.
  • Mastered field-level industrial sensor and actuator wiring, safety interlocks, and IIoT communication gateways.
Siemens TIA Portal PLC LAD & FBD SCADA & HMI Sensor-Actuators
Validated Qualifications

Licenses, Certifications & Honors

Grand Honor • ₹20,000 Cash Award

2nd Prize Winner - Best Project Award (Core Category)

Research & Development (R&D) Cell, SVPCET, Nagpur

Conferred 2nd Prize across competitive core branches for superior technical innovation, embedded hardware realization, and real-time edge AI classification on the Indigenous Integrated Railway Track Monitoring System (ITMS).

COEP

Semiconductor & Manufacturing Workshop

COEP Technological University

Issued: Aug 2026
Credential: EDU-COEP-SM-2026073018
CMOS VLSI DRC Rules
IIT

Semiconductor Devices - Microscopic Control

NPTEL IIT Certification

Issued: Jun 2026
Device Physics & Advanced Characterization
Carrier Drift BJT & MOS Energy Bands
IITB

Electronic Devices Simulation [NGSpice]

WEL Lab, IIT Bombay (NPTEL)

Issued: Jun 2026
Circuit Simulation & Parameter Extraction
NGSpice SPICE Deck VTC Inverter
HIXAA

Internet of Things using ESP32

Hixaa Technologies Pvt Ltd

Issued: Apr 2026
Embedded Sensors & IoT Cloud
ESP32 Sensors Cloud WebSockets
Start a Conversation

Let's Connect & Collaborate

I am actively seeking engineering opportunities in Semiconductor Devices, VLSI Engineering, FPGA RTL Design, Embedded Firmware, and Industrial Automation. Feel free to reach out directly.

ashleshapokale@gmail.com
linkedin.com/in/ashleshampokale
Open
github.com/ashleshampokale
Open
Nagpur, Maharashtra, India (Open to Relocation / Hybrid)

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Ashlesha M. Pokale - Engineering Resume

B.Tech ETC (SVPCET Nagpur) • CGPA 7.70
Core Competencies
Semiconductor Device Characterization (NGSpice, I-V, C-V, MOSFET/CMOS) • FPGA & Digital RTL (Verilog HDL, VHDL, Xilinx Spartan-3E, FSMs) • Embedded Systems (STM32, ARM Cortex-M3, ESP32) • Edge AI (YOLOv8 on Radxa SBC 3-TOPS Vivante NPU) • Industrial Automation (Siemens TIA Portal, PLC LAD/FBD/SFC, SCADA).
Education & Honors
B.Tech in Electronics & Telecommunication (2023 - 2027) at St. Vincent Pallotti College of Engineering & Technology, Nagpur. Cumulative CGPA: 7.70/10.
Award: 2nd Prize Winner (Core Category, ₹20,000 cash prize) for Indigenous Integrated Railway Track Monitoring System (ITMS).
Internships & Research
Research Intern at Maharashtra Remote Sensing Application Centre (MRSAC), Nagpur (Jun 2026): NISAR Satellite SAR & IoT precision agriculture.
Industrial Automation Intern at Siemens CoE, VNIT Nagpur (Jun 2025): PLC programming (LAD, FBD, SFC) and SCADA systems.
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